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000530s2000 nyu b 001 0 eng |
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|a 00044147
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|a 0201675196 (pbk.)
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|a (OCoLC)505700339
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|a (OCoLC)ocn505700339
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|a (NNC)2653313
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|a DLC
|c DLC
|d NNC
|d HR-ZaFER
|b hrv
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|a pcc
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|a QA76.5
|b .F8643 2000
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|a 004.165
|2 21
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1 |
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|a Furber, Stephen B.
|q (Stephen Bo),
|d 1953-
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| 245 |
1 |
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|a ARM system-on-chip architecture /
|c Steve Furber.
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| 260 |
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|a New York :
|b Addison-Wesley,
|c 2000.
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| 263 |
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|a 0008
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| 300 |
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|a xii, 419 str. :
|b ilustr. ;
|c 23 cm.
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| 504 |
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|a Includes bibliographical references and index.
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| 505 |
0 |
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|g 1.
|t An Introduction to Processor Design.
|t Processor architecture and organization.
|t Abstraction in hardware design.
|t MU0 - a simple processor.
|t Instruction set design.
|t Processor design trade-offs.
|t The Reduced Instruction Set Computer.
|t Design for low power consumption --
|g 2.
|t The ARM Architecture.
|t The Acorn RISC Machine.
|t Architectural inheritance.
|t The ARM programmer's model.
|t ARM development tools --
|g 3.
|t ARM Assembly Language Programming.
|t Data processing instructions.
|t Data transfer instructions.
|t Control flow instructions.
|t Writing simple assembly language programs --
|g 4.
|t ARM Organization and Implementation.
|t 3-stage pipeline ARM organization.
|t 5-stage pipeline ARM organization.
|t ARM instruction execution.
|t ARM implementation.
|t The ARM coprocessor interface --
|g 5.
|t The ARM Instruction Set.
|t Exceptions.
|t Conditional execution.
|t Branch and Branch with Link (B, BL).
|t Branch, Branch with Link and eXchange (BX, BLX).
|t Software Interrupt (SWI).
|t Data processing instructions.
|t Multiply instructions.
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| 505 |
8 |
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|t Count leading zeros (CLZ - architecture v5T only).
|t Single word and usigned byte data transfer instructions.
|t Half-word and signed byte data transfer instructions.
|t Multiple register transfer instructions.
|t Swap memory and register instructions (SWP).
|t Status register to status register transfer instructions.
|t General register to status register transfer instructions.
|t Coprocessor instructions.
|t Coprocessor data operations.
|t Coprocessor data transfers.
|t Coprocessor register transfers.
|t Breakpoint instruction (BRK -architecture v5T only).
|t Unused instruction space.
|t Memory faults.
|t ARM architecture variants --
|g 6.
|t Architectural Support for High-Level Languages.
|t Abstraction in software design.
|t Data types.
|t Floating-point data types.
|t The ARM floating-point architecture.
|t Expressions.
|t Conditional statements.
|t Loops.
|t Functions and procedures.
|t Use of memory.
|t Run-time environment --
|g 7.
|t The Thumb Instruction Set.
|t The Thumb bit in the CPSR.
|t The Thumb programmer's model.
|t Thumb branch instructions.
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|t Thumb software interrupt instruction.
|t Thumb data processing instructions.
|t Thumb single register data transfer instructions.
|t Thumb multiple register data transfer instructions.
|t Thumb breakpoint instruction.
|t Thumb implementation.
|t Thumb applications --
|g 8.
|t Architectural Support for System Development.
|t The ARM memory interface.
|t The Advanced Microcontroller Bus Architecture (AMBA).
|t The ARM reference peripheral specification.
|t Hardware system prototyping tools.
|t The ARMulator.
|t The JTAG boundary scan test architecture.
|t The ARM debug architecture.
|t Embedded Trace.
|t Signal processing support --
|g 9.
|t ARM Processor Cores.
|t Arm7tdmi.
|t Arm8.
|t Arm9tdmi.
|t Arm10tdmi.
|t Discussion --
|g 10.
|t Memory Hierarchy.
|t Memory size and speed.
|t On-chip memory.
|t Caches.
|t Cache design - an example.
|t Memory management --
|g 11.
|t Architectural Support for Operating Systems.
|t The ARM system control coprocessor.
|t CP15 protection unit registers.
|t ARM protection unit.
|t CP15 MMU registers.
|t ARM MMU architecture.
|t Synchronization.
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|t Context switching.
|t Input/Output --
|g 12.
|t ARM CPU Cores.
|t The ARM710T, ARM720T and ARM740T.
|t The ARM810.
|t The StrongARM SA-110.
|t The ARM920T and ARM940T.
|t The ARM946E-S and ARM966E-S.
|t The ARM1020E --
|g 13.
|t Embedded ARM Applications.
|t The VLSI Ruby Advanced Communication Processor.
|t The VLSI ISDN Subscriber Processor.
|t The OneC VWS22100 GSM chip.
|t The Ericsson - VLSI Bluetooth Baseband Controller.
|t The ARM7500 and ARM7500FE.
|t The ARM7100.
|t The SA-1100 --
|g 14.
|t The AMULET Asynchronous ARM Processors.
|t Self-timed design.
|t Amulet1.
|t Amulet2.
|t AMULET2e.
|t Amulet3.
|t The DRACO telecommunications controller.
|t A self-timed future?
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| 650 |
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0 |
|a RISC microprocessors.
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| 650 |
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0 |
|a Computer architecture.
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| 900 |
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|a AUTH
|b TOC
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| 942 |
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|2 udc
|c K
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| 999 |
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|c 38325
|d 38325
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