Optimum gate ordering of CMOS logic gates using euler path approach
| Permalink: | http://skupni.nsk.hr/Record/nsk.NSK01000682077/Details |
|---|---|
| Matična publikacija: |
CIT. Journal of computing and information technology 15 (2007), 1 ; str. 85-92 |
| Glavni autor: | Roy, Kuntal (-) |
| Vrsta građe: | Članak |
| Jezik: | eng |
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| 245 | 1 | 0 | |a Optimum gate ordering of CMOS logic gates using euler path approach : |b some insights and explanations / |c Kuntal Roy. |
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| 650 | 7 | |a Komplementarni metal oksid poluvodiči |2 nskps | |
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