Recent results on the implementation of a burst error and burst erasure channel emulator using an FPGA architecture
The behaviour of a transmission channel may be simulated using the performance abilities of current generation multiprocessing hardware, namely, a multicore Central Processing Unit (CPU), a general purpose Graphics Processing Unit (GPU), or a Field Programmable Gate Array (FPGA). These were investig...
| Permalink: | http://skupni.nsk.hr/Record/nsk.NSK01001102375 |
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| Matična publikacija: |
Journal of communications software and systems (Online) 16 (2020), 1 ; str. 19-29 |
| Glavni autori: | Travan, Caterina (Author), Vatta, Francesca, Babich, Fulvio |
| Vrsta građe: | e-članak |
| Jezik: | eng |
| Predmet: | |
| Online pristup: |
https://doi.org/10.24138/jcomss.v16i1.766 Journal of communications software and systems (Online) Hrčak |
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https://doi.org/10.24138/jcomss.v16i1.766Journal of communications software and systems (Online)
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