Seven-level symmetrical series/parallel multilevel inverter with PWM technique using digital logic

This paper attempts to come up with a proposed configuration of Multilevel inverters with a lesser number of switches that are smaller in size, lesser in cost and with a higher efficiency. Designing an inverter topology with a lesser number of switches and proper control technique is the major chall...

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Permalink: http://skupni.nsk.hr/Record/nsk.NSK01001131287/Description
Matična publikacija: International journal of electrical and computer engineering systems (Online)
12 (2021), 3 ; str. 123-130
Glavni autori: Motaparthi, Nagaraju (Author), Kumar Malligunta, Kiran
Vrsta građe: e-članak
Jezik: eng
Predmet:
Online pristup: https://doi.org/10.32985/ijeces.12.3.1
International journal of electrical and computer engineering systems (Online)
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